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HT6542B
Keyboard Controller with PS/2
Features
* * * * * * * *
High reliability MOS technology 8042-type host interface 6MHz-12MHz operating frequency Communicates with keyboard directly Provides enhanced Gate A20 switching
Support PS/2 compatible mouse Auto-detect AT and PS/2 motherboard Support 40 pin DIP and 44 pin PLCC packages
General Description
The HT6542B is a keyboard controller developed by Holtek with a 4-bit microprocessor. It is pin-to-pin compatible with Intel 8042 keyboard controller used in IBM PC's. PC manufacturers need not modify any printed wiring layout when using the HT6542B in lieu of the Intel 8042 based keyboard controller. Furthermore, the HT6542B can support a system clock speed of up to 12MHz. The HT6542B can detect the motherboard type automatically, therefore it can be employed on both of AT and PS/2 motherboard.
Pin Assignment
40 Pin DIP package 44 Pin PLCC package
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HT6542B
Block Diagram
Pin Description
Pin No. (DIP)
1 2,3 4 5,7,11,25 6 8 9 2 3,4 5 1,6,8,12,13, 23,29,34 7 9 10
Pin No. (PLCC)
Pin Name
KBCI OSCI,OSCO RES NC CS RD A0
I/O
I I I -- I I I
Pin Descriptions
Keyboard clock input pin System clock input pin, to generate internal oscillator signal Low level to reset HT6542B. After RES goes to high level HT6542B needs 10ms to initial internal circuit No connection Host-interface chip select, active low Host-interface read signal, active low Host-interface address select input. When high, it selects the command/status registers; when low it selects the data register
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HT6542B
Pin No. (DIP)
10 12~19 20 21 22 23
Pin No. (PLCC)
11 14~21 22 24 25 26
Pin Name
WR D0~D7 VSS RC A20 P22/MSDO
I/O
I
Pin Descriptions
Host-interface write signal, active low
Host interface data bus. An 8-bit bi-directional port I/O for data transfers between the host CPU and the HT6542B -- O O Circuit ground Host-reset control signal output Gate A20 control signal output
General purpose input/output pin for AT I/O motherboard. Mouse data output pin for PS/2 motherboard General purpose input/output pin for AT I/O motherboard. Mouse clock output pin for PS/2 motherboard I Test input pin, for IC test only. Connected to VCC in applications
24
27
P23/MSCO
26
28
TEST
27
30
P10/KBDI
General purpose input/output pin for AT I/O motherboard. Keyboard data input pin for PS/2 motherboard General purpose input/output pin for AT I/O motherboard. Mouse data input pin for PS/2 motherboard I/O General purpose input/output pins Keyboard inhibit input. When low, keyboard is inhibited. When high, keyboard transmission is enabled. Keyboard output buffer full interrupt for AT and PS/2 mother board (active high) Output low for AT mothboard. Mouse output buffer full interrupt for PS/2 mother board (active high). Keyboard clock output pin for AT and PS/2 motherboard. Keyboard data output pin for AT and PS/2 motherboard. Keyboard data input pin for AT motherboard Mouse clock input pin for PS/2 motherboard Positive power supply
28
31 32~33 35~37 38
P11/MSDI
29~33
P12~P16
34
KBD-INH
I
35
39
KB-OBFO
O
36
40
MS-OBFO
O
37 38 39 40
41 42 43 44
KBCO KBDO KBDI/MSCI VDD
O O I --
Absolute Maximum Ratings
Supply Voltage ............................ -0.3V to 5.5V Input Voltage .................. VSS-0.3V to VDD+0.3 Storage Temperature ............... -50C to 125C Operating Temperature ................. 0C to 70C
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HT6542B
D.C. Characteristics
Symbol
VDD IDD VIL VIH
Parameter
Operating Voltage Operating Current Input Low Voltage Input High Voltage P10~P16, KBCI, KBDI, D0~D7, RC, A20, P22, P23, KB-OBFO, MS-OBFO Output Low Voltage IOL=6mA D0~D7, KB-OBFO, MS-OBFO, KBCO, KBDO, A20, RC Output High Voltage IOH=0.3mA P10~P16, KBD-INH Pull-High Resistance KBCI, KBDI, CS, RD, A0, WR Pull-High Resistance
Test Condition VDD
-- 5V -- --
Min.
4.75 -- -0.5 2
Typ.
5 4 -- --
Max.
5.25 6 0.8 VDD
Unit
V mA V V
Condition
- FOSC=8MHz No load -- --
VOL
5V
VOL=0.5V
--
--
0.5
V
VOH
5V
VOH=4.5V
4.5
--
--
V
RPH1 RPH2
-- --
-- --
10 30
20 50
30 70

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HT6542B
Functional Description
Power on
When power is switched on, the HT6542B autodetect the motherboard type(AT or PS/2), then disable the keyboard/mouse and waits for the self-test command to perform a self-test. If no error is detected during self-test, HEX 55 is registered in the output buffer (note that any value other than HEX 55 would indicate HT6542B failure) and the keyboard interface is enabled. The HT6542B is now ready to receive a system command or keyboard data.
Keyboard/mouse data transmission
* b1(IBF): Input buffer full
This bit is set while the system is sending data to the HT6542B's input buffer and cleared when the HT6542B reads the input buffer data.
* b2: System flag
This bit is 0 after power-on reset, set to 1 after self-test OK.
* b3: Command/Data
The keyboard/mouse transmits data to the controller in an 11-bit format in sync, with the keyboard/mouse clock signal. If this transmission is not completed within the specified period, the HT6542B will register HEX FF into the output buffer and set the "transmit timeout" error bit in the STATUS REGISTER to 1.
Controller data transmission
When the system writes the data to the HT6542B from I/O 64H, this bit becomes 1. Reset to 0 if from I/O 60H.
* b4:
This bit reflects the KBD-INH status whenever data is placed in the HT6542B's output buffer.
* b5: Auxiliary Output Buffer Full.
The controller transmits data to the keyboard/mouse in the same manner as it receives data from the keyboard/mouse. When the HT6542B starts transmitting data and the keyboard/mouse does not start receiving (does not start clocking) or data transmission is not completed within 15ms, the HT6542B will register HEX FE into the output buffer and set the "transmit time-out" error bit in the STATUS REGISTER to 1.
Keyboard inhibited (KBD-INH to low)
0: The HT6542B's output buffer is a keyboard data. 1: The HT6542B's output buffer is a mouse data.
* b6: Transmit time-out
Set to 1 when the keyboard or mouse is not able to completely transmite data to the HT6542B within the specified period.
* b7: Parity error
1: The HT6542B has received the keyboard/mouse code with a parity error. (should be odd parity).
Output buffer
If the KBD-INH is switched to low, the keyboard/mouse is inhibited. The HT6542B receive keyboard/mouse code and check the KBD-INH status, if inhibited the keyboard SCAN CODE and mouse code will be ignored and the keyboard/mouse command response is registered into the HT6542B's output buffer.
Status register notations
The output buffer is located in I/O HEX 60. It is used to transmit keyboard/mouse code or keyboard controller response data. The output buffer data is valid only when OBF=1.
Input buffer
The STATUS REGISTER is located in HEX 64 of the I/O. It provides the HT6542B and interface status to the system. The following are the definitions for each bit:
* b0(OBF): Output buffer full
The input buffer is located in I/O HEX 60 or HEX 64. The system writes command and data into this port in the following categories:
* Data written to I/O HEX 64 as command
write.
* Data written to I/O HEX 60 as data write.
This bit is set while the HT6542B is sending data to the output buffer and cleared when the system reads the output buffer(I/O HEX 60H).
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HT6542B
Application Circuit
For AT motherboard (40 pin DIP, for example)
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HT6542B
For PS/2 motherboard (40 pin DIP, for example)
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